PIC18F4620-I/ML【PDF 10/286 页】IC MCU FLASH 32KX16 44QFN

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1996 Microchip Technology Inc.

DS30412C-page 107

PIC17C4X

15.0

INSTRUCTION SET SUMMARY

The PIC17CXX instruction set consists of 58 instruc-

tions. Each instruction is a 16-bit word divided into an

OPCODE and one or more operands. The opcode

species the instruction type, while the operand(s) fur-

ther specify the operation of the instruction. The

PIC17CXX instruction set can be grouped into three

types:

byte-oriented

bit-oriented

literal and control operations.

These formats are shown in Figure 15-1.

Table 15-1 shows the eld descriptions for the

opcodes. These descriptions are useful for under-

standing the opcodes in Table 15-2 and in each spe-

cic instruction descriptions.

byte-oriented instructions, 'f' represents a le regis-

ter designator and 'd' represents a destination designa-

tor. The le register designator species which le

The destination designator species where the result of

the operation is to be placed. If 'd' = '0', the result is

placed in the WREG register. If 'd' = '1', the result is

placed in the le register specied by the instruction.

bit-oriented instructions, 'b' represents a bit eld des-

ignator which selects the number of the bit affected by

the operation, while 'f' represents the number of the le

in which the bit is located.

literal and control operations, 'k' represents an 8- or

11-bit constant or literal value.

The instruction set is highly orthogonal and is grouped

into:

byte-oriented operations

bit-oriented operations

literal and control operations

All instructions are executed within one single instruc-

tion cycle, unless:

a conditional test is true

the program counter is changed as a result of an

instruction

a table read or a table write instruction is exe-

cuted (in this case, the execution takes two

instruction cycles with the second cycle executed

as a NOP)

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 25 MHz, the normal

instruction execution time is 160 ns. If a conditional test

is true or the program counter is changed as a result of

an instruction, the instruction execution time is 320 ns.

TABLE 15-1:

OPCODE FIELD

DESCRIPTIONS

Field

Description

Peripheral register le address (00h to 1Fh)

Table pointer control i = '0' (do not change)

i = '1' (increment after instruction execution)

Table byte select t = '0' (perform operation on lower

byte)

t = '1' (perform operation on upper byte literal eld,

constant data)

WREG

Working register (accumulator)

Bit address within an 8-bit le register

Literal eld, constant data or label

Don't care location (= '0' or '1')

The assembler will generate code with x = '0'. It is

the recommended form of use for compatibility with

all Microchip software tools.

Destination select

0 = store result in WREG

1 = store result in le register f

Default is d = '1'

Unused, encoded as '0'

Destination select

0 = store result in le register f and in the WREG

1 = store result in le register f

Default is s = '1'

label

Label name

C,DC,

Z,OV

ALU status bits Carry, Digit Carry, Zero, Overow

GLINTD

Global Interrupt Disable bit (CPUSTA<4>)

TBLPTR

Table Pointer (16-bit)

TBLAT

Table Latch (16-bit) consists of high byte (TBLATH)

and low byte (TBLATL)

TBLATL

Table Latch low byte

TBLATH

Table Latch high byte

TOS

Top of Stack

Program Counter

BSR

Bank Select Register

WDT

Watchdog Timer Counter

Time-out bit

Power-down bit

dest

Destination either the WREG register or the speci-

ed register le location

[ ]

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